diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-08-12 12:48:58 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-19 18:18:57 +0200 |
| commit | b18a6665df2633193b7863e3dd9eca230536405b (patch) | |
| tree | 12e13454875b1e8b1d6086850a684d55f9d8f61e /src/drivers/intel/fsp2_0/include/fsp | |
| parent | 5bb9e93ea68db0ffe156f2df2d69397f21c57095 (diff) | |
vboot/vbnv_flash: make I/O connection agnostic
There's no need to be SPI specific w.r.t. how the flash is
connected. Therefore, use the RW boot device to write the
contents of VBNV. The erasable check was dropped because that
information isn't available. All regions should be aligned
accordingly on the platform for the underlying hardware
implementation. And once the VBNV region fills the erase
will fail.
BUG=chrome-os-partner:56151
Change-Id: I07fdc8613e0b3884e132a2f158ffeabeaa6da6ce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16206
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/drivers/intel/fsp2_0/include/fsp')
0 files changed, 0 insertions, 0 deletions