diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-11-30 15:50:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-04 10:21:42 +0000 |
| commit | 31218a4259708233c17fa8b09fa9d9c06ea1f2ad (patch) | |
| tree | a1d32df5213f557c61430bc341da1b64aa7f7c4d /src/drivers/intel/fsp2_0/header_display.c | |
| parent | 37cae540343d8f02258c3209f90114e7189753e2 (diff) | |
drivers/intel/fsp2_0: Fix running on x86_64
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/drivers/intel/fsp2_0/header_display.c')
| -rw-r--r-- | src/drivers/intel/fsp2_0/header_display.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index a134fed065..4f9366657d 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -19,24 +19,24 @@ void fsp_print_header_info(const struct fsp_header *hdr) printk(BIOS_SPEW, "Type: %s/%s\n", (hdr->component_attribute & 1) ? "release" : "debug", (hdr->component_attribute & 2) ? "official" : "test"); - printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n", - hdr->image_id, hdr->image_base, hdr->image_size); + printk(BIOS_SPEW, "image ID: %s, base 0x%zx + 0x%zx\n", + hdr->image_id, (size_t)hdr->image_base, (size_t)hdr->image_size); printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n", - hdr->cfg_region_offset, hdr->cfg_region_size); + (size_t)hdr->cfg_region_offset, (size_t)hdr->cfg_region_size); if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { printk(BIOS_SPEW, "\tMemory init offset 0x%zx\n", - hdr->memory_init_entry_offset); + (size_t)hdr->memory_init_entry_offset); } if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { printk(BIOS_SPEW, "\tSilicon init offset 0x%zx\n", - hdr->silicon_init_entry_offset); + (size_t)hdr->silicon_init_entry_offset); if (CONFIG(PLATFORM_USES_FSP2_2)) printk(BIOS_SPEW, "\tMultiPhaseSiInit offset 0x%zx\n", - hdr->multi_phase_si_init_entry_offset); + (size_t)hdr->multi_phase_si_init_entry_offset); printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n", - hdr->notify_phase_entry_offset); + (size_t)hdr->notify_phase_entry_offset); } } |