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| author | Subrata Banik <subrata.banik@intel.com> | 2020-07-31 12:09:11 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-06 04:24:24 +0000 |
| commit | 96b32f194bf6ed4de7d495acc0c50106cf3c72d7 (patch) | |
| tree | d935fc989ffc6ef402153014cdbb90870aef7cac /src/drivers/intel/fsp2_0/Makefile.inc | |
| parent | a3c33c6e21d341bac34612ebb9c6bbef91ad04e1 (diff) | |
drivers/intel/fsp2_0: Do AP re-init after FSP-S if USE_INTEL_FSP_MP_INIT enable
This patch ensures that coreboot is able to take control of APs back
by doing a full AP re-initialization after FSP-S is done.
TEST=Able to see all cores available after booting to OS using below command
when coreboot is built with USE_INTEL_FSP_MP_INIT enable.
> cat /proc/cpuinfo
Without this CL :
shows only 1 core (only BSP)
With this CL :
shows all possible cores available (BSP + APs)
Change-Id: I247d8d1166c77bd01922323b6a0f14ec6640a666
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/drivers/intel/fsp2_0/Makefile.inc')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index e954a462a1..32140f4228 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -14,6 +14,7 @@ romstage-$(CONFIG_MMA) += mma_core.c romstage-y += cbmem.c ramstage-y += debug.c +ramstage-$(CONFIG_USE_INTEL_FSP_MP_INIT) += fsp_mpinit.c ramstage-$(CONFIG_RUN_FSP_GOP) += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c |