diff options
| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-05-28 15:37:37 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-03 13:19:59 +0000 |
| commit | f7f90f7c3f35f03efe037c4e079420e88a317610 (patch) | |
| tree | bd0ac5b7b97d53c0a694948bc4c743dd55e42dfc /src/drivers/intel/fsp1_1 | |
| parent | 7da638c20e4c56bc103be23216862e265b3ca8b1 (diff) | |
drivers/intel/fsp1_1: Exit cleanly if FSP not found
Instead of dereferencing a null pointer, print a nice message and exit
cleanly if the FSP isn't found in the CBFS.
Change-Id: I761e7febc7cec5bd2ef3af214bc51777ee5c313d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1401467, 1401717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33049
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
| -rw-r--r-- | src/drivers/intel/fsp1_1/car.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 82dc320e0e..41a02f33b9 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -160,17 +160,14 @@ void mainboard_romstage_entry(unsigned long bist) { /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram * is still enabled. We can directly access work buffer here. */ - FSP_INFO_HEADER *fih; struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); - if (prog_locate(&fsp)) { - fih = NULL; - printk(BIOS_ERR, "Unable to locate %s\n", prog_name(&fsp)); - } else { - /* This leaks a mapping which this code assumes is benign as - * the flash is memory mapped CPU's address space. */ - fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); - } + if (prog_locate(&fsp)) + die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); + + /* This leaks a mapping which this code assumes is benign as + * the flash is memory mapped CPU's address space. */ + FSP_INFO_HEADER *fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); cache_as_ram_stage_main(fih); } |