diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-01-19 19:19:15 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-29 16:56:01 +0100 |
| commit | fbdc71941454cd4f6dbaebb3e38d27d11ab256ea (patch) | |
| tree | d3a29b03bdd169afffbf00fa67ba09c5d9c3f30c /src/drivers/intel/fsp1_1 | |
| parent | dcc3ecc940e95cb6a97dbea203d3680f67910b59 (diff) | |
intel/skylake: Implement native Cache-as-RAM (CAR)
Now coreboot should do BIOS CAR setup along with NEM
mode setup.
This patch also provides a mechanism to use 16MB code caching
benefit although LLC still limited to 1M/1.5M based
on SOC LLC limit.
Here with unlimited cache line gets replaced. Now we could use
unlimited cache size along with well defined data size
[pg: updated to current upstream #defines]
BUG=chrome-os-partner:48412
BRANCH=glados
TEST=Builds and Boots on FAB4 SKU2/3.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: pchandri <preetham.chandrian@intel.com>
Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b
Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a
Original-Reviewed-on: https://chromium-review.googlesource.com/320855
Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13138
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
| -rw-r--r-- | src/drivers/intel/fsp1_1/Kconfig | 8 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/after_raminit.S | 11 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.inc | 19 |
3 files changed, 21 insertions, 17 deletions
diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index c959e57cd1..9b2c463878 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -23,14 +23,6 @@ if PLATFORM_USES_FSP1_1 comment "Intel FSP 1.1" -config DCACHE_RAM_BASE - hex - default 0xfef00000 - -config DCACHE_RAM_SIZE - hex - default 0x4000 - config HAVE_FSP_BIN bool "Should the Intel FSP binary be added to the flash image" help diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index 85a0a8c200..eb99157959 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -20,7 +20,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -.extern fih_car /* * This is the common entry point after DRAM has been initialized. */ @@ -31,6 +30,14 @@ /* Switch to the stack in RAM */ movl %eax, %esp +#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) + + /* SOC specific NEM */ + #include <soc/car_teardown.S> + +#else +.extern fih_car + post_code(POST_FSP_TEMP_RAM_EXIT) /* Calculate TempRamExit entry into FSP */ @@ -56,8 +63,8 @@ */ movb $0xBC, %ah jmp .Lhlt - 1: +#endif /* Display the MTRRs */ call soc_display_mtrrs diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 35abdb48da..6e7e50b992 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -33,17 +33,22 @@ * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ - - mov %eax, %edi - + movl %eax, %edi cache_as_ram: post_code(0x20) +#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) + /* - * edi: BIST value - * mm0: low 32-bits of TSC value - * mm1: high 32-bits of TSC value + * SOC specific setup + * NOTE: This has to preserve the registers + * mm0, mm1 and edi. */ + #include <soc/car_setup.S> + + post_code(0x28) + +#endif /* * Find the FSP binary in cbfs. @@ -143,7 +148,7 @@ CAR_init_done: rep stosl before_romstage: - post_code(0x23) + post_code(0x2A) /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main |