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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-04 19:54:32 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-07 05:47:33 +0000
commitb2a5f0b9c2eb79f1a9d4fe4f87f1460c1be7fa6d (patch)
tree37b8bd523e8a672853bba15804cb161278824693 /src/drivers/intel/fsp1_1
parentfe481eb3e5e8e8d39d892bfcfe085bc7d49ff886 (diff)
cpu/x86/smm: Promote smm_subregion()
No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/drivers/intel/fsp1_1')
-rw-r--r--src/drivers/intel/fsp1_1/car.c2
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/memmap.h40
-rw-r--r--src/drivers/intel/fsp1_1/raminit.c2
-rw-r--r--src/drivers/intel/fsp1_1/ramstage.c2
-rw-r--r--src/drivers/intel/fsp1_1/stage_cache.c2
5 files changed, 4 insertions, 44 deletions
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 19eb041eac..1b6f62c351 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -19,9 +19,9 @@
#include <commonlib/helpers.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
#include <fsp/car.h>
#include <fsp/util.h>
-#include <fsp/memmap.h>
#include <program_loading.h>
/* platform_enter_postcar() determines the stack to use after
diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h
deleted file mode 100644
index 3f3850f3f5..0000000000
--- a/src/drivers/intel/fsp1_1/include/fsp/memmap.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _COMMON_MEMMAP_H_
-#define _COMMON_MEMMAP_H_
-
-#include <types.h>
-
-/* Fills in the arguments for the entire SMM region covered by chipset
- * protections. e.g. TSEG. */
-void smm_region(void **start, size_t *size);
-
-enum {
- /* SMM handler area. */
- SMM_SUBREGION_HANDLER,
- /* SMM cache region. */
- SMM_SUBREGION_CACHE,
- /* Chipset specific area. */
- SMM_SUBREGION_CHIPSET,
- /* Total sub regions supported. */
- SMM_SUBREGION_NUM,
-};
-
-/* Fills in the start and size for the requested SMM subregion. Returns
- * 0 on susccess, < 0 on failure. */
-int smm_subregion(int sub, void **start, size_t *size);
-
-#endif /* _COMMON_MEMMAP_H_ */
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 21f4ab9b05..2f53957596 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -19,7 +19,7 @@
#include <cf9_reset.h>
#include <commonlib/helpers.h>
#include <console/console.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
#include <fsp/romstage.h>
#include <fsp/util.h>
#include <lib.h> /* hexdump */
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 52a886ce30..049dfd05f0 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -17,7 +17,7 @@
#include <bootmode.h>
#include <arch/acpi.h>
#include <console/console.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
#include <fsp/ramstage.h>
#include <fsp/util.h>
#include <lib.h>
diff --git a/src/drivers/intel/fsp1_1/stage_cache.c b/src/drivers/intel/fsp1_1/stage_cache.c
index 2d594e6048..ab0c1c0126 100644
--- a/src/drivers/intel/fsp1_1/stage_cache.c
+++ b/src/drivers/intel/fsp1_1/stage_cache.c
@@ -15,7 +15,7 @@
*/
#include <console/console.h>
-#include <fsp/memmap.h>
+#include <cpu/x86/smm.h>
#include <stage_cache.h>
void stage_cache_external_region(void **base, size_t *size)