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authorArthur Heymans <arthur@aheymans.xyz>2019-01-06 07:35:11 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-21 17:37:32 +0000
commitbe291e8abf173e4f12e6d9e5532fdf1acbcb9a67 (patch)
tree12b2a0c6bcf03649b81ef38aa033b5bc06f4a7c0 /src/drivers/intel/fsp1_1/temp_ram_exit.c
parentf91344cd07a4e9a4c2e183f00431b4fee05daf33 (diff)
soc/intel/fsp1.1: Implement postcar stage
This moves FSP1.1 to use postcar stage to tear down CAR. On platforms with USE_GENERIC_FSP_CAR_INC the FSP header is found during the postcar stage so there is no need to push to save it in CAR global variables. On FSP1.1 platforms with an open source CAR implementation (Skylake, even though it still runs the FSP-T), the soc/intel/common/blocks/cpu/car/exit_car.S code tears down CAR. This also uses common functions to set up the MTRR to use after CAR is torn down. Test: build/boot on google/celes (BSW) and google/chell (SKL) Change-Id: I2330993842aae9c1365230f0c6bd8a2449dc73a5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/temp_ram_exit.c')
-rw-r--r--src/drivers/intel/fsp1_1/temp_ram_exit.c44
1 files changed, 44 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/temp_ram_exit.c b/src/drivers/intel/fsp1_1/temp_ram_exit.c
new file mode 100644
index 0000000000..c1535e0bc0
--- /dev/null
+++ b/src/drivers/intel/fsp1_1/temp_ram_exit.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+
+asmlinkage void chipset_teardown_car_main(void)
+{
+ FSP_INFO_HEADER *fih;
+ uint32_t status;
+ FSP_TEMP_RAM_EXIT temp_ram_exit;
+ struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
+
+ if (prog_locate(&fsp)) {
+ die("Unable to locate fsp.bin\n");
+ } else {
+ /* This leaks a mapping which this code assumes is benign as
+ * the flash is memory mapped CPU's address space. */
+
+ /* FIXME: the implementation of find_fsp is utter garbage
+ as it casts error values to FSP_INFO_HEADER pointers.
+ Checking for return values can only be done sanely once
+ that is fixed. */
+ fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp)));
+ }
+
+ temp_ram_exit = (FSP_TEMP_RAM_EXIT)(fih->TempRamExitEntryOffset +
+ fih->ImageBase);
+ printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit);
+ status = temp_ram_exit(NULL);
+
+ if (status != FSP_SUCCESS) {
+ printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status);
+ die("TempRamExit returned an error!\n");
+ }
+}