diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/drivers/intel/fsp1_1/ramstage.c | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/ramstage.c')
| -rw-r--r-- | src/drivers/intel/fsp1_1/ramstage.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 864ab4509f..814bddf007 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -55,7 +55,7 @@ static void display_hob_info(FSP_INFO_HEADER *fsp_info_header) int missing_hob = 0; void *hob_list_ptr = get_hob_list(); - if (!IS_ENABLED(CONFIG_DISPLAY_HOBS)) + if (!CONFIG(DISPLAY_HOBS)) return; /* Verify the HOBs */ @@ -117,12 +117,12 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) soc_silicon_init_params(&silicon_init_params); /* Locate VBT and pass to FSP GOP */ - if (IS_ENABLED(CONFIG_RUN_FSP_GOP)) + if (CONFIG(RUN_FSP_GOP)) load_vbt(is_s3_wakeup, &silicon_init_params); mainboard_silicon_init_params(&silicon_init_params); /* Display the UPD data */ - if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) + if (CONFIG(DISPLAY_UPD_DATA)) soc_display_silicon_init_params(original_params, &silicon_init_params); @@ -139,7 +139,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); /* Mark graphics init done after SiliconInit if VBT was provided */ -#if IS_ENABLED(CONFIG_RUN_FSP_GOP) +#if CONFIG(RUN_FSP_GOP) /* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs * to be #if'd out instead of using if (). */ if (silicon_init_params.GraphicsConfigPtr) @@ -152,10 +152,10 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) static void fsp_cache_save(struct prog *fsp) { - if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP)) + if (CONFIG(DISPLAY_SMM_MEMORY_MAP)) smm_memory_map(); - if (IS_ENABLED(CONFIG_NO_STAGE_CACHE)) + if (CONFIG(NO_STAGE_CACHE)) return; printk(BIOS_DEBUG, "FSP: Saving binary in cache\n"); @@ -192,7 +192,7 @@ void fsp_load(void) if (load_done) return; - if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) { + if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) { printk(BIOS_DEBUG, "FSP: Loading binary from cache\n"); stage_cache_load_stage(STAGE_REFCODE, &fsp); } else { |