diff options
| author | Keith Short <keithshort@chromium.org> | 2019-05-16 14:07:43 -0600 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-05-22 16:53:19 +0000 |
| commit | bb41aba0d8c3c3cbfee44b0f7267e78fb7d012ee (patch) | |
| tree | 66c4acc7abb2d19c37dbe8d470a87d64a0637631 /src/drivers/intel/fsp1_1/raminit.c | |
| parent | 1835bf0fd4b77ab3eae1fb085be1667d13ed3144 (diff) | |
post_code: add post code for invalid vendor binary
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/raminit.c')
| -rw-r--r-- | src/drivers/intel/fsp1_1/raminit.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 726cc26a0c..fc6f848089 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -195,9 +195,6 @@ void raminit(struct romstage_params *params) } #if CONFIG(DISPLAY_HOBS) - if (hob_list_ptr == NULL) - die("ERROR - HOB pointer is NULL!\n"); - /* * Verify that FSP is generating the required HOBs: * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 @@ -244,7 +241,10 @@ void raminit(struct romstage_params *params) "ERROR - Missing one or more required FSP HOBs!\n"); /* Display the HOBs */ - print_hob_type_structure(0, hob_list_ptr); + if (hob_list_ptr != NULL) + print_hob_type_structure(0, hob_list_ptr); + else + printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n"); #endif /* Get the address of the CBMEM region for the FSP reserved memory */ @@ -274,14 +274,16 @@ void raminit(struct romstage_params *params) printk(BIOS_DEBUG, "0x%08x: Chipset reserved bytes reported by FSP\n", (unsigned int)delta_bytes); - die("Please verify the chipset reserved size\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "Please verify the chipset reserved size\n"); } #endif } /* Verify the FSP 1.1 HOB interface */ if (fsp_verification_failure) - die("ERROR - coreboot's requirements not met by FSP binary!\n"); + die_with_post_code(POST_INVALID_VENDOR_BINARY, + "ERROR - coreboot's requirements not met by FSP binary!\n"); /* Display the memory configuration */ report_memory_config(); |