diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2015-09-11 13:51:38 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-11-20 18:21:25 +0100 |
| commit | b90b94d3efbbe969c019ab8bb8316e2c08ac4968 (patch) | |
| tree | 66b36427232d4408f6706d00295837ec57bb3767 /src/drivers/intel/fsp1_1/raminit.c | |
| parent | fb128734ec45b9ca7d3ed1a59ea05a81fa6ae360 (diff) | |
intel: Add MMA feature in coreboot
This patch implements Memory Margin Analysis feature in coreboot.
Few things to note
(1) the feature is enabled by setting CONFIG_MMA=y in the config file
(2) coreboot reads mma_test_metadata.bin from cbfs during romstage and
gets the name of MMA test name and test config name. Then coreboot finds
these files in CBFS.
If found, coreboot passes location and size of these files to FSP via
UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test
would be executed during memory init.
(3) FSP passes MMA results data in HOB and coreboot saves it in cbmem
(4) when system boots to OS after test is executed cbmem tool is used
to grab the MMA results data.
BRANCH=none
BUG=chrome-os-partner:43731
TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests
Not tested on Glados
CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479
Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7
Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/299476
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/12481
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/raminit.c')
| -rw-r--r-- | src/drivers/intel/fsp1_1/raminit.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index c4b5b21b23..50704a8389 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -19,6 +19,7 @@ #include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> +#include <soc/intel/common/mma.h> #include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> @@ -98,6 +99,10 @@ void raminit(struct romstage_params *params) /* Update the UPD data */ soc_memory_init_params(params, &memory_init_params); mainboard_memory_init_params(params, &memory_init_params); + + if (IS_ENABLED(CONFIG_MMA)) + setup_mma(&memory_init_params); + post_code(0x36); /* Display the UPD data */ |