diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2019-04-05 13:42:14 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-11 11:57:55 +0000 |
| commit | 1385b7dd10385e8ae58b4d988701af1eac060fd3 (patch) | |
| tree | 63ef17f64c8d495228ec6e4abe30ec9a0fad7de2 /src/drivers/intel/fsp1_1/raminit.c | |
| parent | dd11810367e6a66fb9366d108cb0bb6b1664355a (diff) | |
drivers/intel/fsp1_1: Configure UART after memory init
FSP code will default enable the onboard serial port.
When external serial port is used, this onboard port needs to be
disabled.
Add function mainboard_after_memory_init() function to perform
required actions to re-enabled output to external serial port.
BUG=N/A
TEST=LPC Post card on Intel Cherry Hill
Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/raminit.c')
| -rw-r--r-- | src/drivers/intel/fsp1_1/raminit.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 2dd5c77e96..8405c943aa 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -125,6 +125,7 @@ void raminit(struct romstage_params *params) timestamp_add_now(TS_FSP_MEMORY_INIT_START); post_code(POST_FSP_MEMORY_INIT); status = fsp_memory_init(&fsp_memory_init_params); + mainboard_after_memory_init(); post_code(0x37); timestamp_add_now(TS_FSP_MEMORY_INIT_END); @@ -322,3 +323,9 @@ __weak void soc_memory_init_params( { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } + +/* Initialize the SoC after MemoryInit */ +__weak void mainboard_after_memory_init(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} |