diff options
author | Aaron Durbin <adurbin@chromium.org> | 2015-09-24 12:26:31 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@gmail.com> | 2015-10-11 23:55:45 +0000 |
commit | e6af4be1587f34f2f79d6e8b9ece94cfa7cd4c8e (patch) | |
tree | 94503e1a9526b30ff2356357d4a91a4e89900034 /src/drivers/intel/fsp1_1/include/fsp | |
parent | cc5ac17fab97bd16f3122bb492fbdc28644c8567 (diff) |
intel fsp1_1: prepare for romstage vboot verification split
In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:
- Add fsp/car.h to house the declarations for functions in
the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
romstage separated from cache-as-ram as well as one that
is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
soc/intel/{braswell,common,skylake}.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/include/fsp')
-rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/car.h | 52 | ||||
-rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/util.h | 7 |
2 files changed, 52 insertions, 7 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h new file mode 100644 index 0000000000..8234b37ea8 --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef FSP1_1_CAR_H +#define FSP1_1_CAR_H + +#include <arch/cpu.h> +#include <fsp/api.h> +#include <stdint.h> + +/* cache-as-ram support for FSP 1.1. */ +struct cache_as_ram_params { + uint64_t tsc; + uint32_t bist; + FSP_INFO_HEADER *fih; + uintptr_t bootloader_car_start; + uintptr_t bootloader_car_end; +}; + +/* Entry points from the cache-as-ram assembly code. */ +asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params); +asmlinkage void after_cache_as_ram(void *chipset_context); +/* Per stage calls from the above two functions. The void * return from + * cache_as_ram_stage_main() is the stack pointer to use in ram after + * exiting cache-as-ram mode. */ +void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih); +void after_cache_as_ram_stage(void); + +/* Mainboard and SoC initialization prior to console. */ +void car_mainboard_pre_console_init(void); +void car_soc_pre_console_init(void); +/* Mainboard and SoC initialization post console initialization. */ +void car_mainboard_post_console_init(void); +void car_soc_post_console_init(void); + +#endif diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 0919c660d0..b3772a2598 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -28,13 +28,6 @@ #include <program_loading.h> #include <commonlib/region.h> -/* cache-as-ram context for FSP 1.1. */ -struct fsp_car_context { - FSP_INFO_HEADER *fih; - uintptr_t bootloader_car_start; - uintptr_t bootloader_car_end; -}; - /* find_fsp() should only be called from assembly code. */ FSP_INFO_HEADER *find_fsp(uintptr_t fsp_base_address); /* Set FSP's runtime information. */ |