diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2016-11-18 14:36:34 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-12-13 18:00:43 +0100 |
| commit | ffc934d9440b5a8dabcedb4da0fa88d9a1e65e18 (patch) | |
| tree | 2fd448d09b9a9c87ffbc6700f8ea25112f024e73 /src/drivers/intel/fsp1_1/include/fsp/romstage.h | |
| parent | fa97cefbb3fad90573459e57845b658c9d3351a2 (diff) | |
intel MMA: Enable MMA with FSP2.0
- Separate mma code for fsp1.1 and fsp2.0
and restructuring the code
- common code is placed in mma.c and mma.h
- mma_fsp<ver>.h and fsp<ver>/mma_core.c contains
fsp version specific code.
- whole MMA feature is guarded by CONFIG_MMA flag.
Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/17496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/include/fsp/romstage.h')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/romstage.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 4683f5e5a2..dc1b6a66b0 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2016 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,6 +23,7 @@ #include <fsp/car.h> #include <fsp/util.h> #include <soc/intel/common/util.h> +#include <soc/intel/common/mma.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> /* chip_power_state */ @@ -80,6 +81,8 @@ void raminit(struct romstage_params *params); void report_memory_config(void); void romstage_common(struct romstage_params *params); asmlinkage void *romstage_main(FSP_INFO_HEADER *fih); +/* Initialize memory margin analysis settings. */ +void setup_mma(MEMORY_INIT_UPD *memory_upd); void *setup_stack_and_mtrrs(void); void soc_after_ram_init(struct romstage_params *params); void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -87,5 +90,8 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); void soc_pre_ram_init(struct romstage_params *params); +/* Update the SOC specific memory config param for mma. */ +void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, + struct mma_config_param *mma_cfg); #endif /* _COMMON_ROMSTAGE_H_ */ |