diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-24 08:03:37 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-27 13:50:11 +0200 |
| commit | ae738acdc5f02d232e035538c67d63ba19b9ccaa (patch) | |
| tree | 862a877545dad919c698b48381a115bd15130fcc /src/drivers/intel/fsp1_1/include/fsp/romstage.h | |
| parent | 7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b (diff) | |
cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/include/fsp/romstage.h')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/romstage.h | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index d07dc375c8..4683f5e5a2 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -88,11 +88,4 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); void soc_pre_ram_init(struct romstage_params *params); -/* - * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs. - * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data. - */ -asmlinkage void *soc_set_mtrrs(void *top_of_stack); -asmlinkage void soc_enable_mtrrs(void); - #endif /* _COMMON_ROMSTAGE_H_ */ |