diff options
| author | Nico Huber <nico.h@gmx.de> | 2019-05-04 16:59:20 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-07 15:55:50 +0000 |
| commit | 66318aad07e6810065bc0668f4a1f34b7cb77687 (patch) | |
| tree | 6b55edcdc8f54bf0d0f65365cd7ee0ccb5fe2884 /src/drivers/intel/fsp1_1/include/fsp/romstage.h | |
| parent | 99e836c843e6a8536348d5cc9581b5a17512a263 (diff) | |
intel/fsp1_1: Move MRC cache pointers into `romstage_params`
These are part of a common concept and not SoC specific.
Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/include/fsp/romstage.h')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/romstage.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index d608484999..4e95dadadf 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -18,6 +18,7 @@ #ifndef _COMMON_ROMSTAGE_H_ #define _COMMON_ROMSTAGE_H_ +#include <stddef.h> #include <stdint.h> #include <arch/cpu.h> #include <memory_info.h> @@ -32,6 +33,15 @@ struct romstage_params { struct chipset_power_state *power_state; struct pei_data *pei_data; void *chipset_context; + + /* Fast boot and S3 resume MRC data */ + size_t saved_data_size; + const void *saved_data; + bool disable_saved_data; + + /* New save data from MRC */ + size_t data_to_save_size; + const void *data_to_save; }; /* |