drivers/intel/{fsp1_1,fsp2_0}: Provide separate function for fsp load

Add a function to allow FSP component loading separately from silicon
initialization. This enables SoCs that might not have stage cache
available during silicon initialization to load/save components from/to
stage cache before it is relocated or destroyed.

BUG=chrome-os-partner:63114
BRANCH=None
TEST=Compiles successfully.

Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18413
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 6 insertions, 0 deletions

diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
index 5ce6aa8892..a9f6a8db22 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
@@ -21,6 +21,12 @@
 #include <soc/intel/common/util.h>
 #include <stdint.h>
 
+/*
+ * Load FSP from stage cache or CBFS. This allows SoCs to load FSP separately
+ * from calling silicon init. It might be required in cases where stage cache is
+ * no longer available by the point SoC calls into silicon init.
+ */
+void fsp_load(void);
 /* Perform Intel silicon init. */
 void intel_silicon_init(void);
 void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);