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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-10 00:23:58 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-29 10:15:24 +0000
commitd0bc92df73d7653ed8b6c76baf3a39c7f8f37173 (patch)
tree9d4eaa1787fb8a016c841a661bec9f0171314190 /src/drivers/intel/fsp1_1/include/fsp/ramstage.h
parentae38035d3a6c8892bf734bac19ddf052365e9b4c (diff)
intel/fsp1_1: Declare fsp_load() as static
The function has only one local call-site. Change-Id: I623953796e6cd3a8e5b4f72293d953b61f14a5a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49999 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/include/fsp/ramstage.h')
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/ramstage.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
index 0a6295edc5..f925088e00 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
@@ -6,12 +6,6 @@
#include <fsp/util.h>
#include <stdint.h>
-/*
- * Load FSP from stage cache or CBFS. This allows SoCs to load FSP separately
- * from calling silicon init. It might be required in cases where stage cache is
- * no longer available by the point SoC calls into silicon init.
- */
-void fsp_load(void);
/* Perform Intel silicon init. */
void intel_silicon_init(void);
void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);