diff options
| author | Wim Vervoorn <wvervoorn@eltan.com> | 2019-12-16 14:21:09 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-20 17:50:28 +0000 |
| commit | 67117c3971f16e4b47e927821a19f110b4885111 (patch) | |
| tree | 321d4462a87aaeed64b8926df22a5cf0085c80c5 /src/drivers/intel/fsp1_1/include/fsp/ramstage.h | |
| parent | 0e45b2875add588ddada7f40e294db99d62c3c3c (diff) | |
{drivers,soc}/intel/fsp1_1: Move chipset specific logo handling to SoC
FSP logo handling used PcdLogoPtr and PcdLogoSize which are elements of
the chipset specific FSP structures.
Create soc_load_logo() which will pass the logo pointer and size.
This function will call fsp_load_logo which will load the logo.
BUG=NA
TEST= Build and verified logo is displayed on Facebook FBG1701
Change-Id: I86943e64ca1ddd05e7e88fc6b882cfd33b98272e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37791
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/include/fsp/ramstage.h')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h index a5eac0e279..e50edd8773 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -26,6 +26,7 @@ void fsp_load(void); /* Perform Intel silicon init. */ void intel_silicon_init(void); void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup); +const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size); /* Called after the silicon init code has run. */ void soc_after_silicon_init(void); /* Initialize UPD data before SiliconInit call. */ @@ -33,7 +34,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params); void mainboard_silicon_init_params(SILICON_INIT_UPD *params); void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new); -void load_logo(SILICON_INIT_UPD *params); +const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params); void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params); #endif /* _INTEL_COMMON_RAMSTAGE_H_ */ |