diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-06-16 14:33:30 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-06-24 17:03:49 +0200 |
| commit | 4a8c19cc90464ad215395bd116c9dc95fc682cac (patch) | |
| tree | 3ce82af088b0bbb782d667a531f54641abeb1dfb /src/drivers/intel/fsp1_1/cache_as_ram.inc | |
| parent | bfdf2489f071d8ee1d1c510e503b488526111eb7 (diff) | |
FSP 1.1: Bring source up-to-date
Use 3rdparty/blobs subdirectory for binary files
Display the MTRRs after TempRamExit and before the MTRR setup
Clear all of the variable MTRRs before the MTRR setup
Define the FSP attributes location and bits
Properly display the FSP_RESERVED_MEMORY_RESOURCE_HOB and the
FSP_BOOTLOADER_TOLUM_HOB.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: I788a5f1e7676b1a06c1bcd66ddbd0a2249cad47c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10589
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/cache_as_ram.inc')
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.inc | 45 |
1 files changed, 42 insertions, 3 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 4a0827d2df..f56d841380 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -204,12 +204,51 @@ before_romstage: cmp $0, %eax jne halt3 - /* Get number of MTRRs. */ + /* Display the MTRRs */ + call soc_display_mtrrs + + /* + * The stack contents are initialized in src/soc/intel/common/stack.c + * to be the following: + * + * * + * * + * * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * +0: Number of variable MTRRs to clear + */ + + /* Clear all of the variable MTRRs. */ popl %ebx movl $MTRRphysBase_MSR(0), %ecx + clr %eax + clr %edx + 1: testl %ebx, %ebx jz 1f + wrmsr /* Write MTRR base. */ + inc %ecx + wrmsr /* Write MTRR mask. */ + inc %ecx + dec %ebx + jmp 1b + +1: + /* Get number of MTRRs. */ + popl %ebx + movl $MTRRphysBase_MSR(0), %ecx +2: + testl %ebx, %ebx + jz 2f /* Low 32 bits of MTRR base. */ popl %eax @@ -227,8 +266,8 @@ before_romstage: inc %ecx dec %ebx - jmp 1b -1: + jmp 2b +2: post_code(0x39) /* And enable cache again after setting MTRRs. */ |