diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-11-22 14:53:57 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-12-03 14:17:51 +0100 |
| commit | fb509830085e379cee8eb9b5f619c34c249c9d77 (patch) | |
| tree | 6ef8091fb064c4485267082995ac858ee28cc477 /src/drivers/intel/fsp1_1/cache_as_ram.inc | |
| parent | 590ac64d5571d8b85e0ddd65b25b8cda9354de15 (diff) | |
intel/fsp: Add post codes for FSP phases
Add post codes for the various FSP phases and use them as appropriate
in FSP 1.0 and 1.1 implementations.
This will make it more consistent to debug FSP hangs and resets.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados and chell
Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547
Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313822
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/cache_as_ram.inc')
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 7d68f3210f..35abdb48da 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -65,7 +65,7 @@ find_fsp_ret: cmp $CONFIG_FSP_LOC, %eax jbe halt1 - post_code(0x22) + post_code(POST_FSP_TEMP_RAM_INIT) /* Calculate entry into FSP */ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ |