diff options
| author | Frans Hendriks <fhendriks@eltan.com> | 2020-11-20 10:52:39 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-22 22:17:43 +0000 |
| commit | c022a795033062ed1b1908d18fa419444e42aceb (patch) | |
| tree | 7299ab7501a3971fc78f2610efc90be1d5281a6c /src/drivers/intel/fsp1_1/cache_as_ram.S | |
| parent | 335eb1219c73032eee92462f76d508233fb97b55 (diff) | |
drivers/intel/fsp1_1: Add function to report FSP-T output
This allows to compare the FSP-T output in %ecx and %edx to coreboot's
CAR symbols.
Tested on Facebook FBG1701
Change-Id: Ice748e542180f6e1dc1505e7f37b6b6c68772bda
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/cache_as_ram.S')
| -rw-r--r-- | src/drivers/intel/fsp1_1/cache_as_ram.S | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index b5b47ce9a6..f2d29aa4a8 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -145,6 +145,14 @@ CAR_init_done: * mm1: high 32-bits of TSC value */ + /* + * temp_memory_start/end reside in the .bss section, which gets cleared + * below. Save the FSP return value to the stack before writing those + * variables. + */ + push %ecx + push %edx + /* clear .bss section */ cld xor %eax, %eax @@ -154,6 +162,11 @@ CAR_init_done: shrl $2, %ecx rep stosl + pop %edx + movl %edx, temp_memory_end + pop %ecx + movl %ecx, temp_memory_start + /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp |