diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/drivers/intel/fsp1_1/after_raminit.S | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers/intel/fsp1_1/after_raminit.S')
| -rw-r--r-- | src/drivers/intel/fsp1_1/after_raminit.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index cdc8e9381f..3f2a7ae02f 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -30,7 +30,7 @@ /* Switch to the stack in RAM */ movl %eax, %esp -#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) +#if CONFIG(SKIP_FSP_CAR) /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car @@ -87,7 +87,7 @@ * +0: Number of variable MTRRs to clear */ -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) +#if CONFIG(SOC_SETS_MSRS) push %esp call soc_set_mtrrs @@ -147,7 +147,7 @@ post_code(0x3a) -#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) +#if CONFIG(SOC_SETS_MSRS) call soc_enable_mtrrs #else /* Enable MTRR. */ |