diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-24 08:03:37 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-27 13:50:11 +0200 |
| commit | ae738acdc5f02d232e035538c67d63ba19b9ccaa (patch) | |
| tree | 862a877545dad919c698b48381a115bd15130fcc /src/drivers/intel/fsp1_1/after_raminit.S | |
| parent | 7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b (diff) | |
cpu/x86: Support CPUs without rdmsr/wrmsr instructions
Quark does not support the rdmsr and wrmsr instructions. In this case
use a SOC specific routine to support the setting of the MTRRs. Migrate
the code from FSP 1.1 to be x86 CPU common.
Since all rdmsr/wrmsr accesses are being converted, fix the build
failure for quark in lib/reg_script.c. Move the soc_msr_x routines and
their depencies from romstage/mtrr.c to reg_access.c.
TEST=Build and run on Galileo Gen2
Change-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15839
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/intel/fsp1_1/after_raminit.S')
| -rw-r--r-- | src/drivers/intel/fsp1_1/after_raminit.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index 122c0bf03e..618e989a8c 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -87,7 +87,7 @@ * +0: Number of variable MTRRs to clear */ -#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) +#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) push %esp call soc_set_mtrrs @@ -136,7 +136,7 @@ dec %ebx jmp 2b 2: -#endif /* CONFIG_SOC_SETS_MTRRS */ +#endif /* CONFIG_SOC_SETS_MSRS */ post_code(0x39) @@ -147,7 +147,7 @@ post_code(0x3a) -#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) +#if IS_ENABLED(CONFIG_SOC_SETS_MSRS) call soc_enable_mtrrs #else /* Enable MTRR. */ @@ -155,7 +155,7 @@ rdmsr orl $MTRR_DEF_TYPE_EN, %eax wrmsr -#endif /* CONFIG_SOC_SETS_MTRRS */ +#endif /* CONFIG_SOC_SETS_MSRS */ post_code(0x3b) |