diff options
| author | Martin Roth <martinroth@google.com> | 2015-11-18 16:07:54 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-23 18:49:54 +0100 |
| commit | c5bb7bd957f57428760edf26d41a6626b10a894e (patch) | |
| tree | 7c30e638df22dd3d3bca9a0737b6d7ad6aaba514 /src/drivers/intel/fsp1_0 | |
| parent | 40d073c3c5d17aa877dc08f8ec600979ed155363 (diff) | |
fsp1_0: Update Kconfig for symbols not depending on FSP binary
There were several symbols that were inside the 'if HAVE_FSP_BIN' that
don't really depend on having the FSP binary. In theory, we should be
able to build a coreboot rom and add the FSP binary later. This doesn't
always work in practice, but this is a step in that direction.
This also fixes a Kconfig warning for Rangeley.
Change-Id: I327d8fe5231d7de25f2a74b8a193deb47e4c5ee1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12461
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/drivers/intel/fsp1_0')
| -rw-r--r-- | src/drivers/intel/fsp1_0/Kconfig | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 36bfa7c58e..28df90e987 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -41,6 +41,8 @@ config FSP_FILE help The path and filename of the Intel FSP binary for this platform. +endif #HAVE_FSP_BIN + config FSP_LOC hex "Intel FSP Binary location in CBFS" help @@ -92,8 +94,6 @@ config VIRTUAL_ROM_SIZE the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM size is 16 MB. -endif #HAVE_FSP_BIN - config CACHE_ROM_SIZE_OVERRIDE hex "Cache ROM Size" default CBFS_SIZE |