diff options
| author | Rob Barnes <robbarnes@google.com> | 2022-01-13 20:54:14 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-17 15:54:03 +0000 |
| commit | 5a8b9c94a640f740069e6cdead26737d6ac20c69 (patch) | |
| tree | 1f7ba2f0aea6268bf420a735964eee5b255c605b /src/drivers/i2c/tpm/cr50.c | |
| parent | 57309d362cbd00b63f77d839a09dba58eb558615 (diff) | |
cr50: Increase cr50 i2c probe timeout
Turns out 150ms isn't enough in the worst reset conditions. On guybrush
the TPM is reset in S0i3 and the CR50 is allowed to hibernate. The CR50
is woken up and initialized early during S0i3 resume. Occasionally the
CR50 isn't ready before the probe times out.
BUG=b:213828947
BRANCH=None
TEST=suspend_stress_test -c 1000
Change-Id: Ifda438080cf1ad2796c7061223a6a97b8e6e9987
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'src/drivers/i2c/tpm/cr50.c')
| -rw-r--r-- | src/drivers/i2c/tpm/cr50.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index a8a310fc7f..6c3471dfa7 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -445,13 +445,13 @@ static int cr50_i2c_probe(struct tpm_chip *chip, uint32_t *did_vid) int retries; /* - * 150 ms should be enough to synchronize with the TPM even under the + * 200 ms should be enough to synchronize with the TPM even under the * worst nested reset request conditions. In vast majority of cases * there would be no wait at all. */ printk(BIOS_INFO, "Probing TPM I2C: "); - for (retries = 15; retries > 0; retries--) { + for (retries = 20; retries > 0; retries--) { int rc; rc = cr50_i2c_read(chip, TPM_DID_VID(0), (uint8_t *)did_vid, 4); |