diff options
author | Ben Chuang <benchuanggli@gmail.com> | 2020-07-16 11:34:36 +0800 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2020-08-05 15:16:16 +0000 |
commit | 026e940f03107cdd32b6f479134d1b61f700a3de (patch) | |
tree | e9e5ddb277253c2ddd24a597fad9806dc2ed7189 /src/drivers/genesyslogic/gl9763e/gl9763e.h | |
parent | e2497d0181f5ab20d012c761400601b15565ce58 (diff) |
drivers/genesyslogic/gl9763e: Add driver for Genesys Logic GL9763E
The device is a PCIe to eMMC bridge controller to be used in the
Chromebook as the boot disk. The datasheet name is GL9763E and
the revision is 02.
The patch sets single request AXI, disables ASPM L0s and enables SSC.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I158c79f5ac6e559f335b6b50092469c7b1646c56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/drivers/genesyslogic/gl9763e/gl9763e.h')
-rw-r--r-- | src/drivers/genesyslogic/gl9763e/gl9763e.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.h b/src/drivers/genesyslogic/gl9763e/gl9763e.h new file mode 100644 index 0000000000..fd9c6ba5c2 --- /dev/null +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Definitions for Genesys Logic GL9763E */ + +#include <types.h> + +#define VHS 0x884 +#define VHS_REV_MASK (0xF << 16) +#define VHS_REV_R (0x0 << 16) +#define VHS_REV_M (0x1 << 16) +#define VHS_REV_W (0x2 << 16) +#define SCR 0x8E0 +#define SCR_AXI_REQ BIT(9) + +#define CFG_REG_2 0x8A4 +#define CFG_REG_2_L0S BIT(11) + +#define PLL_CTL 0x938 +#define PLL_CTL_SSC BIT(19) + +#define PLL_CTL_2 0x93C +#define PLL_CTL_2_MAX_SSC_MASK (0xFFFF << 16) +#define MAX_SSC_30000PPM (0xF5C3 << 16) |