diff options
| author | Ben Chuang <benchuanggli@gmail.com> | 2022-03-18 15:56:31 +0800 |
|---|---|---|
| committer | Martin L Roth <martinroth@google.com> | 2022-03-22 03:45:30 +0000 |
| commit | 15854c91341458222f1ac9801fa21c9dd830fb13 (patch) | |
| tree | 2c24e533a8c3f3e24b1f8784f44cffa6ccb19005 /src/drivers/genesyslogic/gl9763e/gl9763e.c | |
| parent | e8c186cdef27f33cbe022a8ef53d4802f1dc71c9 (diff) | |
drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
Add an option to set L1 entry delay to Max for GL9763E. The L1 entry
delay will be changed to expected value by sdhci-pci-gli driver in
Linux v5.14.
BUG=b:220079865
TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is
0x3FF.
Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Reviewed-by: Martin L Roth <martinroth@google.com>
Diffstat (limited to 'src/drivers/genesyslogic/gl9763e/gl9763e.c')
| -rw-r--r-- | src/drivers/genesyslogic/gl9763e/gl9763e.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c index 4dcfbdcbd0..a4842e81c3 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.c +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c @@ -23,6 +23,11 @@ static void gl9763e_init(struct device *dev) pci_or_config32(dev, SCR, SCR_AXI_REQ); /* Disable L0s support */ pci_and_config32(dev, CFG_REG_2, ~CFG_REG_2_L0S); + + if (CONFIG(DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX)) + /* Set L1 entry delay to MAX */ + pci_or_config32(dev, CFG_REG_2, CFG_REG_2_L1DLY_MAX); + /* Set SSC to 30000 ppm */ pci_update_config32(dev, PLL_CTL_2, ~PLL_CTL_2_MAX_SSC_MASK, MAX_SSC_30000PPM); /* Enable SSC */ |