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authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-11-03 13:24:14 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-11-09 07:39:05 +0000
commit5145e23a3510b6c6129b5e8aa56876fcfcb1adb6 (patch)
treee43284e625a8c051c9b410f536ab2a64cb90f401 /src/drivers/generic/ioapic
parent8a78f5903952f1dee3ecbde8b8ea613c78639d48 (diff)
soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
All wakes by a PCH PCIe root port were lumped under one event source; this commit splits them up so each root port gets its own ID in the event log. BUG=b:172279061 BRANCH=volteer Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/drivers/generic/ioapic')
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