diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-22 15:24:48 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-28 09:18:18 +0000 |
| commit | 73c967665b6347490a22371c558f34c022836181 (patch) | |
| tree | f53f66951fcdd8235f77e0a16fb1340e434a54b0 /src/drivers/generic/bayhub/bh720.c | |
| parent | a4ecf9654e5ee84958dc8dfea3c1391da61bd263 (diff) | |
bayhub bh720: Factor out common HS200 init code
Except for one debug print in sarien, both functions are identical.
Move them to driver code to avoid unnecessary redundancy.
Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/drivers/generic/bayhub/bh720.c')
| -rw-r--r-- | src/drivers/generic/bayhub/bh720.c | 48 |
1 files changed, 46 insertions, 2 deletions
diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c index 24386642eb..40788cd31d 100644 --- a/src/drivers/generic/bayhub/bh720.c +++ b/src/drivers/generic/bayhub/bh720.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/device.h> +#include <device/mmio.h> #include <device/path.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -11,8 +12,50 @@ #include "chip.h" #include "bh720.h" -__attribute__((weak)) void board_bh720(struct device *dev) +static void bh720_program_hs200_mode(struct device *dev) { + u32 sdbar; + u32 bh720_pcr_data; + + sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1); + + /* Enable Memory Access Function */ + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000); + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000000); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + + /* Set EMMC VCCQ 1.8V PCR 0x308[4] */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_EMMC_SETTING); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_EMMC_SETTING_1_8V); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING); + + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_CSR); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + write32((void *)(sdbar + BH720_MEM_RW_DATA), + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_CSR); + + /* Disable Memory Access */ + write32((void *)(sdbar + BH720_MEM_RW_DATA), 0x80000001); + write32((void *)(sdbar + BH720_MEM_RW_ADR), 0x800000D0); + write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000); } static void bh720_init(struct device *dev) @@ -43,7 +86,8 @@ static void bh720_init(struct device *dev) pci_read_config32(dev, BH720_LINK_CTRL)); } - board_bh720(dev); + if (config && !config->disable_hs200_mode) + bh720_program_hs200_mode(dev); if (config && config->vih_tuning_value) { /* Tune VIH */ |