diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-29 13:25:07 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-10-05 11:00:36 +0000 |
| commit | d02bb67dd62e340bb09b3f629cf60a47a1e1adc8 (patch) | |
| tree | b4106bd7904ed68ebea69dd818db745a7531233e /src/drivers/crb/tpm.h | |
| parent | 598c0dda158bd2062442cbf0b42214d5ed95006f (diff) | |
drivers/crb: Initialize Intel PTT control area
On newer systems such as Alder Lake it has been noticed that Intel PTT
control area is not writable until PTT is switched to ready state. The
EDK2 CRB drivers always initialize the command/response buffer address
and size registers before invoking the TPM command. See STEP 2 in
PtpCrbTpmCommand function in
tianocore/edk2/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
Doing the same in coreboot allowed to perform PTT TPM startup
successfully and measure the components to PCRs in ramstage on an
Alder Lake S platform.
TEST=Enable measured boot and see Intel PTT is started successfully
and no errors occur during PCR extends on MSI PRO Z690-A DDR4 WIFI.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia8e473ecc1a520851d6d48ccad9da35c6f91005d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63957
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'src/drivers/crb/tpm.h')
| -rw-r--r-- | src/drivers/crb/tpm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/drivers/crb/tpm.h b/src/drivers/crb/tpm.h index c43beb6843..be26be2d24 100644 --- a/src/drivers/crb/tpm.h +++ b/src/drivers/crb/tpm.h @@ -33,6 +33,7 @@ #define CRB_REG_CMD_ADDR 0x5C #define CRB_REG_RESP_SIZE 0x64 #define CRB_REG_RESP_ADDR 0x68 +#define CRB_REG_DATA_BUFF 0x80 /* CRB INTF BIT MASK */ #define CRB_INTF_REG_CAP_CRB (1<<14) |