binaryPI: Drop CAR teardown without POSTCAR_STAGE

The remaining (active) binaryPI boards moved away from
BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now.

As the cache_as_ram.S is also used with AGESA, this slightly
reduces the codesize there for romstage and postcar as well.

This commit is actually a revert for the vendorcode parts,
AMD originally shipped the codes using 'invd' for the CAR
teardown, but these were changed for coreboot due the
convoluted teardown that used to happen with non-empty stack.

Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

3 files changed, 39 insertions, 58 deletions

diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc
index fb46d91991..dfb385da80 100644
--- a/src/drivers/amd/agesa/Makefile.inc
+++ b/src/drivers/amd/agesa/Makefile.inc
@@ -20,7 +20,7 @@ romstage-y += state_machine.c
 ramstage-y += state_machine.c
 
 cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S
-postcar-y += cache_as_ram.S
+postcar-y += exit_car.S
 
 romstage-y += def_callouts.c
 romstage-y += eventlog.c
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
index dcb0c43d8e..3f1358a2f8 100644
--- a/src/drivers/amd/agesa/cache_as_ram.S
+++ b/src/drivers/amd/agesa/cache_as_ram.S
@@ -27,7 +27,6 @@
 
 .code32
 .globl _cache_as_ram_setup, _cache_as_ram_setup_end
-.globl chipset_teardown_car
 
 _cache_as_ram_setup:
 
@@ -105,66 +104,11 @@ _cache_as_ram_setup:
 	pushl	%eax
 	call	romstage_main
 
-#if CONFIG(POSTCAR_STAGE)
-
-/* We do not return. Execution continues with run_postcar_phase()
- * calling to chipset_teardown_car below.
- */
-	jmp	postcar_entry_failure
-
-chipset_teardown_car:
-
-/*
- * Retrieve return address from stack as it will get trashed below if
- * execution is utilizing the cache-as-ram stack.
- */
-	pop	%esp
-
-#else
-
-	movl	%eax, %esp
-
-/* Register %esp is new stacktop for remaining of romstage. */
-
-#endif
-
-	/* Disable cache */
-	movl	%cr0, %eax
-	orl	$CR0_CacheDisable, %eax
-	movl	%eax, %cr0
-
-/* Register %esp is preserved in AMD_DISABLE_STACK. */
-	AMD_DISABLE_STACK
-
-#if CONFIG(POSTCAR_STAGE)
-
-	jmp	*%esp
-
-#else
-
-	/* enable cache */
-	movl	%cr0, %eax
-	andl	$0x9fffffff, %eax
-	movl	%eax, %cr0
-
-	call	romstage_after_car
-
-#endif
-
 	/* Should never see this postcode */
-	post_code(0xaf)
+	post_code(0xae)
 
 stop:
 	hlt
 	jmp	stop
 
-/* These are here for linking purposes. */
-.weak early_all_cores, romstage_main
-early_all_cores:
-romstage_main:
-postcar_entry_failure:
-	/* Should never see this postcode */
-	post_code(0xae)
-	jmp	stop
-
 _cache_as_ram_setup_end:
diff --git a/src/drivers/amd/agesa/exit_car.S b/src/drivers/amd/agesa/exit_car.S
new file mode 100644
index 0000000000..f9d056e599
--- /dev/null
+++ b/src/drivers/amd/agesa/exit_car.S
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <gcccar.inc>
+#include <cpu/x86/cache.h>
+
+.code32
+.globl chipset_teardown_car
+
+chipset_teardown_car:
+	pop	%esp
+
+	/* Disable cache */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	AMD_DISABLE_STACK
+
+	/* enable cache */
+	movl	%cr0, %eax
+	andl	$(~(CR0_CD | CR0_NW)), %eax
+	movl	%eax, %cr0
+
+	jmp	*%esp