diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-29 07:30:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-07 12:54:39 +0000 |
| commit | bab9e2e6bdf3bbfa6047773a04632e0fbdf64afb (patch) | |
| tree | ab42496f77d4bf76f3f9f79eea16ddc92d8a5cd6 /src/drivers/amd/agesa | |
| parent | 11cac784ff788b4f0495758d7f5992e457ea552c (diff) | |
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/drivers/amd/agesa')
| -rw-r--r-- | src/drivers/amd/agesa/romstage.c | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 35b2778e68..82ef31ebd3 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -13,6 +13,7 @@ #include <smp/node.h> #include <string.h> #include <timestamp.h> +#include <romstage_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> @@ -31,16 +32,12 @@ static void fill_sysinfo(struct sysinfo *cb) */ static void ap_romstage_main(void); -static void romstage_main(void) +void __noreturn romstage_main(void) { struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; int cbmem_initted = 0; - timestamp_add_now(TS_ROMSTAGE_START); - - console_init(); - printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n", initial_lapicid(), cpuid_eax(1)); @@ -79,6 +76,7 @@ static void romstage_main(void) prepare_and_run_postcar(); /* We do not return. */ + die("failed to load postcar\n"); } static void ap_romstage_main(void) @@ -96,11 +94,6 @@ static void ap_romstage_main(void) halt(); } -asmlinkage void car_stage_entry(void) -{ - romstage_main(); -} - void *cbmem_top_chipset(void) { /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ |