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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-11-24 16:32:05 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-11 22:47:10 +0000 |
| commit | 1b12b64dab57151d1f04d13d09c1afbf16a7485f (patch) | |
| tree | a912c3447ddc7528fa320d8c254c8b403e79cb55 /src/drivers/amd/agesa/romstage.c | |
| parent | b643d3df8adbc933e02d8c8c7dcc61cc60b65afb (diff) | |
AGESA, binaryPI: implement C bootblock
Modify CAR setup to work in bootblock. Provide bootblock C file with
necessary C bootblock functions. Additionally chache the ROM and set
the MMCONF base before jumping to bootblock main.
Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36914
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/amd/agesa/romstage.c')
| -rw-r--r-- | src/drivers/amd/agesa/romstage.c | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 48a81c57df..dbf8bd6070 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <amdblocks/biosram.h> #include <arch/acpi.h> #include <arch/cpu.h> #include <arch/romstage.h> @@ -26,6 +27,8 @@ #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> +void __weak board_BeforeAgesa(struct sysinfo *cb) { } + void __weak platform_once(struct sysinfo *cb) { board_BeforeAgesa(cb); @@ -39,6 +42,11 @@ static void fill_sysinfo(struct sysinfo *cb) agesa_set_interface(cb); } +/* APs will enter directly here from bootblock, bypassing verstage + * and potential fallback / normal bootflow detection. + */ +static void ap_romstage_main(void); + static void romstage_main(void) { struct postcar_frame pcf; @@ -48,13 +56,15 @@ static void romstage_main(void) int cbmem_initted = 0; /* Enable PCI MMIO configuration. */ - amd_initmmio(); + if (CONFIG(ROMCC_BOOTBLOCK)) + amd_initmmio(); fill_sysinfo(cb); if (initial_apic_id == 0) { - timestamp_init(timestamp_get()); + if (CONFIG(ROMCC_BOOTBLOCK)) + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); platform_once(cb); @@ -65,6 +75,9 @@ static void romstage_main(void) printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1)); + if (!CONFIG(ROMCC_BOOTBLOCK)) + set_ap_entry_ptr(ap_romstage_main); + agesa_execute_state(cb, AMD_INIT_RESET); agesa_execute_state(cb, AMD_INIT_EARLY); @@ -105,7 +118,8 @@ static void ap_romstage_main(void) struct sysinfo *cb = &romstage_state; /* Enable PCI MMIO configuration. */ - amd_initmmio(); + if (CONFIG(ROMCC_BOOTBLOCK)) + amd_initmmio(); fill_sysinfo(cb); @@ -117,6 +131,7 @@ static void ap_romstage_main(void) halt(); } +#if CONFIG(ROMCC_BOOTBLOCK) /* This wrapper enables easy transition away from ROMCC_BOOTBLOCK * keeping changes in cache_as_ram.S easy to manage. */ @@ -129,3 +144,9 @@ asmlinkage void ap_bootblock_c_entry(void) { ap_romstage_main(); } +#else +asmlinkage void car_stage_entry(void) +{ + romstage_main(); +} +#endif |