diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-11-24 16:32:05 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-11 22:47:10 +0000 |
| commit | 1b12b64dab57151d1f04d13d09c1afbf16a7485f (patch) | |
| tree | a912c3447ddc7528fa320d8c254c8b403e79cb55 /src/drivers/amd/agesa/cache_as_ram.S | |
| parent | b643d3df8adbc933e02d8c8c7dcc61cc60b65afb (diff) | |
AGESA, binaryPI: implement C bootblock
Modify CAR setup to work in bootblock. Provide bootblock C file with
necessary C bootblock functions. Additionally chache the ROM and set
the MMCONF base before jumping to bootblock main.
Change-Id: I29916a96f490ff717c69dc7cd565d74a83dbfb0d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36914
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/drivers/amd/agesa/cache_as_ram.S')
| -rw-r--r-- | src/drivers/amd/agesa/cache_as_ram.S | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 4417e64595..1034992e17 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -27,9 +27,17 @@ .code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end +.global bootblock_pre_c_entry _cache_as_ram_setup: +/* + * on entry: + * mm0: BIST (ignored) + * mm2_mm1: timestamp at bootblock_protected_mode_entry + */ +bootblock_pre_c_entry: + post_code(0xa0) AMD_ENABLE_STACK @@ -51,8 +59,10 @@ _cache_as_ram_setup: and $0xfffffff0, %esp sub $8, %esp - pushl $0 /* tsc[63:32] */ - pushl $0 /* tsc[31:0] */ + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ post_code(0xa2) |