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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-02-28 00:24:15 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2012-03-31 11:54:37 +0200
commit325b92f64a62f355715a45470e41407ce3c39c1e (patch)
treea86107ccafc56b5a879d554cea975965bba3f7e2 /src/devices
parent5a660ca2293cbf4c1ae44a2f37f9f389124eb749 (diff)
Intel cpus: cache actual size of the Flash ROM device
Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory. Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary. Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/641 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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