device/dram: Reformat code

Most of these changes are suggested by clang-format(13.0-54) tool on
Debian testing.

Change-Id: I9bf5f516db4f12ffe1e9a714c7a8ae179c12b149
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

4 files changed, 72 insertions, 136 deletions

diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index 2ade8ef098..2cacc853c9 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -26,9 +26,8 @@
  */
 int spd_dimm_is_registered_ddr2(enum spd_dimm_type_ddr2 type)
 {
-	if ((type == SPD_DDR2_DIMM_TYPE_RDIMM)
-			|| (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM)
-			|| (type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM))
+	if ((type == SPD_DDR2_DIMM_TYPE_RDIMM) || (type == SPD_DDR2_DIMM_TYPE_72B_SO_RDIMM) ||
+			(type == SPD_DDR2_DIMM_TYPE_MINI_RDIMM))
 		return 1;
 
 	return 0;
@@ -144,8 +143,7 @@ static int spd_decode_tck_time(u32 *tck, u8 c)
 		break;
 	case 0xe:
 	case 0xf:
-		printk(BIOS_WARNING, "Invalid tck setting. "
-			"lower nibble is 0x%x\n", c & 0xf);
+		printk(BIOS_WARNING, "Invalid tck setting. lower nibble is 0x%x\n", c & 0xf);
 		return CB_ERR;
 	default:
 		low = (c & 0xf) * 10;
@@ -336,8 +334,7 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
 
 	reg8 = spd[62];
 	if ((reg8 & 0xf0) != 0x10) {
-		printk(BIOS_ERR, "Unsupported SPD revision %01x.%01x\n",
-			reg8 >> 4, reg8 & 0xf);
+		printk(BIOS_ERR, "Unsupported SPD revision %01x.%01x\n", reg8 >> 4, reg8 & 0xf);
 		dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
 		return SPD_STATUS_INVALID;
 	}
@@ -355,18 +352,15 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
 
 	dimm->row_bits = spd[3];
 	printram("  Rows               : %u\n", dimm->row_bits);
-	if ((dimm->row_bits > 31) ||
-	    ((dimm->row_bits > 15) && (dimm->rev < 0x13))) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid number of memory rows\n");
+	if ((dimm->row_bits > 31) || ((dimm->row_bits > 15) && (dimm->rev < 0x13))) {
+		printk(BIOS_WARNING, "SPD decode: invalid number of memory rows\n");
 		ret = SPD_STATUS_INVALID_FIELD;
 	}
 
 	dimm->col_bits = spd[4];
 	printram("  Columns            : %u\n", dimm->col_bits);
 	if (dimm->col_bits > 15) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid number of memory columns\n");
+		printk(BIOS_WARNING, "SPD decode: invalid number of memory columns\n");
 		ret = SPD_STATUS_INVALID_FIELD;
 	}
 
@@ -390,8 +384,7 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
 	dimm->banks = spd[17];
 	printram("  Banks              : %u\n", dimm->banks);
 	if (!dimm->banks) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid module banks count\n");
+		printk(BIOS_WARNING, "SPD decode: invalid module banks count\n");
 		ret = SPD_STATUS_INVALID_FIELD;
 	}
 
@@ -427,20 +420,17 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
 
 	dimm->cas_supported = spd[18];
 	if ((dimm->cas_supported & 0x3) || !dimm->cas_supported) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid CAS support advertised.\n");
+		printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n");
 		ret = SPD_STATUS_INVALID_FIELD;
 	}
 	printram("  Supported CAS mask : 0x%x\n", dimm->cas_supported);
 
 	if ((dimm->rev < 0x13) && (dimm->cas_supported & 0x80)) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid CAS support advertised.\n");
+		printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n");
 		ret = SPD_STATUS_INVALID_FIELD;
 	}
 	if ((dimm->rev < 0x12) && (dimm->cas_supported & 0x40)) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid CAS support advertised.\n");
+		printk(BIOS_WARNING, "SPD decode: invalid CAS support advertised.\n");
 		ret = SPD_STATUS_INVALID_FIELD;
 	}
 
@@ -449,59 +439,43 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
 
 	/* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */
 	if (spd_decode_tck_time(&dimm->cycle_time[cl], spd[9]) != CB_SUCCESS) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid min tCL for CAS%d\n", cl);
+		printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl);
 		ret = SPD_STATUS_INVALID_FIELD;
 	}
 	/* SDRAM Access from Clock */
-	if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10])
-			!= CB_SUCCESS) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid min tAC for CAS%d\n", cl);
+	if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10]) != CB_SUCCESS) {
+		printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl);
 		ret = SPD_STATUS_INVALID_FIELD;
 	}
 
 	if (dimm->cas_supported & (1 << (cl - 1))) {
 		/* Minimum Clock Cycle at CLX-1 */
-		if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23])
-				!= CB_SUCCESS) {
-			printk(BIOS_WARNING,
-				"SPD decode: invalid min tCL for CAS%d\n",
-				cl - 1);
+		if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23]) != CB_SUCCESS) {
+			printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl - 1);
 			ret = SPD_STATUS_INVALID_FIELD;
 		}
 		/* Maximum Data Access Time (tAC) from Clock at CLX-1 */
-		if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24])
-				!= CB_SUCCESS) {
-			printk(BIOS_WARNING,
-				"SPD decode: invalid min tAC for CAS%d\n",
-				cl - 1);
+		if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24]) != CB_SUCCESS) {
+			printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl - 1);
 			ret = SPD_STATUS_INVALID_FIELD;
 		}
 	}
 	if (dimm->cas_supported & (1 << (cl - 2))) {
 		/* Minimum Clock Cycle at CLX-2 */
-		if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25])
-				!= CB_SUCCESS) {
-			printk(BIOS_WARNING,
-				"SPD decode: invalid min tCL for CAS%d\n",
-				cl - 2);
+		if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25]) != CB_SUCCESS) {
+			printk(BIOS_WARNING, "SPD decode: invalid min tCL for CAS%d\n", cl - 2);
 			ret = SPD_STATUS_INVALID_FIELD;
 		}
 		/* Maximum Data Access Time (tAC) from Clock at CLX-2 */
-		if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26])
-				!= CB_SUCCESS) {
-			printk(BIOS_WARNING,
-				"SPD decode: invalid min tAC for CAS%d\n",
-				cl - 2);
+		if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26]) != CB_SUCCESS) {
+			printk(BIOS_WARNING, "SPD decode: invalid min tAC for CAS%d\n", cl - 2);
 			ret = SPD_STATUS_INVALID_FIELD;
 		}
 	}
 
 	reg8 = (spd[31] >> 5) | (spd[31] << 3);
 	if (!reg8) {
-		printk(BIOS_WARNING,
-			"SPD decode: invalid rank density.\n");
+		printk(BIOS_WARNING, "SPD decode: invalid rank density.\n");
 		ret = SPD_STATUS_INVALID_FIELD;
 	}
 
@@ -557,7 +531,7 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
 		ret = SPD_STATUS_INVALID_FIELD;
 	dimm->flags.self_refresh = (spd[12] >> 7) & 1;
 	printram("The assembly supports self refresh: %s\n",
-		 dimm->flags.self_refresh ? "true" : "false");
+			dimm->flags.self_refresh ? "true" : "false");
 
 	/* Number of PLLs on DIMM */
 	if (dimm->rev >= 0x11)
@@ -598,8 +572,7 @@ int spd_decode_ddr2(struct dimm_attr_ddr2_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
 	printram("  ECC support        : %x\n", dimm->flags.is_ecc);
 
 	dimm->flags.stacked = !!(spd[5] & 0x10);
-	printram("  Package            : %s\n",
-	    dimm->flags.stacked ? "stack" : "planar");
+	printram("  Package            : %s\n", dimm->flags.stacked ? "stack" : "planar");
 
 	if (spd_size > 71) {
 		memcpy(&dimm->manufacturer_id, &spd[64], 4);
diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
index b99730d45b..2bdfd46c6b 100644
--- a/src/device/dram/ddr3.c
+++ b/src/device/dram/ddr3.c
@@ -29,9 +29,8 @@
  */
 int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type)
 {
-	if ((type == SPD_DDR3_DIMM_TYPE_RDIMM)
-	    | (type == SPD_DDR3_DIMM_TYPE_MINI_RDIMM)
-	    | (type == SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM))
+	if ((type == SPD_DDR3_DIMM_TYPE_RDIMM) | (type == SPD_DDR3_DIMM_TYPE_MINI_RDIMM) |
+			(type == SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM))
 		return 1;
 
 	return 0;
@@ -104,8 +103,8 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
 	u16 crc, spd_crc;
 	u8 capacity_shift, bus_width;
 	u8 reg8;
-	u32 mtb;		/* medium time base */
-	u32 ftb;		/* fine time base */
+	u32 mtb; /* medium time base */
+	u32 ftb; /* fine time base */
 	unsigned int val;
 
 	ret = SPD_STATUS_OK;
@@ -233,13 +232,13 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
 	/* Capacity is 256Mbit multiplied by the power of 2 specified in
 	 * capacity_shift
 	 * The rest is the JEDEC formula */
-	dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width
-			 * dimm->ranks) / dimm->width;
+	dimm->size_mb =
+		((1 << (capacity_shift + (25 - 20))) * bus_width * dimm->ranks) / dimm->width;
 
 	/* Medium Timebase =
 	 *   Medium Timebase (MTB) Dividend /
 	 *   Medium Timebase (MTB) Divisor */
-	mtb = (((u32) spd[10]) << 8) / spd[11];
+	mtb = (((u32)spd[10]) << 8) / spd[11];
 
 	/* SDRAM Minimum Cycle Time (tCKmin) */
 	dimm->tCK = spd[12] * mtb;
@@ -281,23 +280,22 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
 		/* Fine timebase (1/256 ps) =
 		 *   Fine Timebase (FTB) Dividend /
 		 *   Fine Timebase (FTB) Divisor */
-		ftb = (((u16) spd[9] & 0xf0) << 4) / (spd[9] & 0x0f);
+		ftb = (((u16)spd[9] & 0xf0) << 4) / (spd[9] & 0x0f);
 
 		/* SPD recommends to round up the MTB part and use a negative
 		 * FTB, so a negative rounding should be always safe */
 
 		/* SDRAM Minimum Cycle Time (tCKmin) correction */
-		dimm->tCK += (s32)((s8) spd[34] * ftb - 500) / 1000;
+		dimm->tCK += (s32)((s8)spd[34] * ftb - 500) / 1000;
 		/* Minimum CAS Latency Time (tAAmin) correction */
-		dimm->tAA += (s32)((s8) spd[35] * ftb - 500) / 1000;
+		dimm->tAA += (s32)((s8)spd[35] * ftb - 500) / 1000;
 		/* Minimum RAS# to CAS# Delay Time (tRCDmin) correction */
-		dimm->tRCD += (s32)((s8) spd[36] * ftb - 500) / 1000;
+		dimm->tRCD += (s32)((s8)spd[36] * ftb - 500) / 1000;
 		/* Minimum Row Precharge Delay Time (tRPmin) correction */
-		dimm->tRP += (s32)((s8) spd[37] * ftb - 500) / 1000;
+		dimm->tRP += (s32)((s8)spd[37] * ftb - 500) / 1000;
 		/* Minimum Active to Active/Refresh Delay Time (tRCmin) corr. */
-		dimm->tRC += (s32)((s8) spd[38] * ftb - 500) / 1000;
-	}
-	else {
+		dimm->tRC += (s32)((s8)spd[38] * ftb - 500) / 1000;
+	} else {
 		printram(" no\n");
 	}
 
@@ -347,8 +345,7 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
 	reg8 = spd[32];
 	if (reg8 & 0x80)
 		dimm->flags.therm_sensor = 1;
-	printram("  Thermal sensor     : %s\n",
-		 dimm->flags.therm_sensor ? "yes" : "no");
+	printram("  Thermal sensor     : %s\n", dimm->flags.therm_sensor ? "yes" : "no");
 
 	/*  SDRAM Device Type */
 	printram("  Standard SDRAM     : %s\n", (spd[33] & 0x80) ? "no" : "yes");
@@ -356,8 +353,7 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
 	if (spd[63] & 0x01) {
 		dimm->flags.pins_mirrored = 1;
 	}
-	printram("  Rank1 Address bits : %s\n",
-			(spd[63] & 0x01) ? "mirrored" : "normal");
+	printram("  Rank1 Address bits : %s\n", (spd[63] & 0x01) ? "mirrored" : "normal");
 
 	dimm->reference_card = spd[62] & 0x1f;
 	printram("  DIMM Reference card: %c\n", 'A' + dimm->reference_card);
@@ -394,13 +390,12 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd)
  *		SPD_STATUS_INVALID_FIELD -- A field with an invalid value was
  *					    detected.
  */
-int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm,
-		       spd_raw_data spd,
-		       enum ddr3_xmp_profile profile)
+int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd,
+			enum ddr3_xmp_profile profile)
 {
 	int ret;
-	u32 mtb;		/* medium time base */
-	u8 *xmp;		/* pointer to XMP profile data */
+	u32 mtb; /* medium time base */
+	u8 *xmp; /* pointer to XMP profile data */
 
 	/* need a valid SPD */
 	ret = spd_decode_ddr3(dimm, spd);
@@ -427,7 +422,7 @@ int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm,
 		/* Medium Timebase =
 		 *   Medium Timebase (MTB) Dividend /
 		 *   Medium Timebase (MTB) Divisor */
-		mtb = (((u32) spd[180]) << 8) / spd[181];
+		mtb = (((u32)spd[180]) << 8) / spd[181];
 
 		dimm->dimms_per_channel = ((spd[178] >> 2) & 0x3) + 1;
 	} else {
@@ -442,13 +437,12 @@ int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm,
 		/* Medium Timebase =
 		 *   Medium Timebase (MTB) Dividend /
 		 *   Medium Timebase (MTB) Divisor */
-		mtb = (((u32) spd[182]) << 8) / spd[183];
+		mtb = (((u32)spd[182]) << 8) / spd[183];
 
 		dimm->dimms_per_channel = ((spd[178] >> 4) & 0x3) + 1;
 	}
 
-	printram("  Max DIMMs/channel  : %u\n",
-			dimm->dimms_per_channel);
+	printram("  Max DIMMs/channel  : %u\n", dimm->dimms_per_channel);
 
 	printram("  XMP Revision       : %u.%u\n", spd[179] >> 4, spd[179] & 0xf);
 
@@ -503,8 +497,7 @@ int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm,
  *
  * @return CB_SUCCESS if DIMM info was written
  */
-enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
-			     const u16 selected_freq,
+enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq,
 			     const struct dimm_attr_ddr3_st *info)
 {
 	struct memory_info *mem_info;
@@ -518,8 +511,7 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
 	if (!mem_info) {
 		mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
 
-		printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n",
-				mem_info);
+		printk(BIOS_DEBUG, "CBMEM entry for DIMM info: %p\n", mem_info);
 		if (!mem_info)
 			return CB_ERR;
 
@@ -527,8 +519,7 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
 	}
 
 	if (mem_info->dimm_cnt >= ARRAY_SIZE(mem_info->dimm)) {
-		printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n",
-			__func__);
+		printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n", __func__);
 		return CB_ERR;
 	}
 
@@ -635,6 +626,5 @@ void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm)
 	if (dimm->tCWL)
 		print_ns("  tCWLmin           : ", dimm->tCWL);
 	if (dimm->tCMD)
-		printk(BIOS_INFO, "  tCMDmin           : %3u\n",
-		       DIV_ROUND_UP(dimm->tCMD, 256));
+		printk(BIOS_INFO, "  tCMDmin           : %3u\n", DIV_ROUND_UP(dimm->tCMD, 256));
 }
diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c
index f8fe8d3a96..050857ee20 100644
--- a/src/device/dram/ddr4.c
+++ b/src/device/dram/ddr4.c
@@ -35,41 +35,13 @@ struct ddr4_speed_attr {
  *                 May be 1 less than the actual max MT/s
  */
 static const struct ddr4_speed_attr ddr4_speeds[] = {
-	[DDR4_1600] = {
-		.min_clock_mhz = 668,
-		.max_clock_mhz = 800,
-		.reported_mts = 1600
-	},
-	[DDR4_1866] = {
-		.min_clock_mhz = 801,
-		.max_clock_mhz = 934,
-		.reported_mts = 1866
-	},
-	[DDR4_2133] = {
-		.min_clock_mhz = 935,
-		.max_clock_mhz = 1067,
-		.reported_mts = 2133
-	},
-	[DDR4_2400] = {
-		.min_clock_mhz = 1068,
-		.max_clock_mhz = 1200,
-		.reported_mts = 2400
-	},
-	[DDR4_2666] = {
-		.min_clock_mhz = 1201,
-		.max_clock_mhz = 1333,
-		.reported_mts = 2666
-	},
-	[DDR4_2933] = {
-		.min_clock_mhz = 1334,
-		.max_clock_mhz = 1466,
-		.reported_mts = 2933
-	},
-	[DDR4_3200] = {
-		.min_clock_mhz = 1467,
-		.max_clock_mhz = 1600,
-		.reported_mts = 3200
-	}
+	[DDR4_1600] = {.min_clock_mhz =  668, .max_clock_mhz =  800, .reported_mts = 1600},
+	[DDR4_1866] = {.min_clock_mhz =  801, .max_clock_mhz =  934, .reported_mts = 1866},
+	[DDR4_2133] = {.min_clock_mhz =  935, .max_clock_mhz = 1067, .reported_mts = 2133},
+	[DDR4_2400] = {.min_clock_mhz = 1068, .max_clock_mhz = 1200, .reported_mts = 2400},
+	[DDR4_2666] = {.min_clock_mhz = 1201, .max_clock_mhz = 1333, .reported_mts = 2666},
+	[DDR4_2933] = {.min_clock_mhz = 1334, .max_clock_mhz = 1466, .reported_mts = 2933},
+	[DDR4_3200] = {.min_clock_mhz = 1467, .max_clock_mhz = 1600, .reported_mts = 3200}
 };
 
 typedef enum {
@@ -95,14 +67,15 @@ const spd_block spd_blocks[] = {
 	{.type = BLOCK_0, 0, 128, 126},   {.type = BLOCK_1, 128, 128, 126},
 	{.type = BLOCK_1_L, 128, 64, 0},  {.type = BLOCK_1_H, 192, 64, 0},
 	{.type = BLOCK_2_L, 256, 64, 62}, {.type = BLOCK_2_H, 320, 64, 0},
-	{.type = BLOCK_3, 384, 128, 0} };
+	{.type = BLOCK_3, 384, 128, 0}
+};
 
 static bool verify_block(const spd_block *block, spd_raw_data spd)
 {
 	uint16_t crc, spd_crc;
 
-	spd_crc = (spd[block->start + block->crc_start + 1] << 8)
-		  | spd[block->start + block->crc_start];
+	spd_crc = (spd[block->start + block->crc_start + 1] << 8) |
+		  spd[block->start + block->crc_start];
 	crc = ddr_crc16(&spd[block->start], block->len - 2);
 
 	return spd_crc == crc;
diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c
index 11808e2cf3..b6246ae660 100644
--- a/src/device/dram/spd.c
+++ b/src/device/dram/spd.c
@@ -47,7 +47,7 @@ static void convert_default_module_type_to_spd_info(struct spd_info *info)
 }
 
 static void convert_ddr2_module_type_to_spd_info(enum ddr2_module_type module_type,
-		struct spd_info *info)
+						 struct spd_info *info)
 {
 	switch (module_type) {
 	case DDR2_SPD_RDIMM:
@@ -75,7 +75,7 @@ static void convert_ddr2_module_type_to_spd_info(enum ddr2_module_type module_ty
 }
 
 static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_type,
-		struct spd_info *info)
+						 struct spd_info *info)
 {
 	switch (module_type) {
 	case DDR3_SPD_RDIMM:
@@ -104,7 +104,7 @@ static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_ty
 }
 
 static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_type,
-		struct spd_info *info)
+						 struct spd_info *info)
 {
 	switch (module_type) {
 	case DDR4_SPD_RDIMM:
@@ -129,7 +129,7 @@ static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_ty
 }
 
 static void convert_ddr5_module_type_to_spd_info(enum ddr5_module_type module_type,
-		struct spd_info *info)
+						 struct spd_info *info)
 {
 	switch (module_type) {
 	case DDR5_SPD_RDIMM:
@@ -158,7 +158,7 @@ static void convert_ddr5_module_type_to_spd_info(enum ddr5_module_type module_ty
 }
 
 static void convert_lpx_module_type_to_spd_info(enum lpx_module_type module_type,
-		struct spd_info *info)
+						struct spd_info *info)
 {
 	switch (module_type) {
 	case LPX_SPD_NONDIMM:
@@ -203,7 +203,7 @@ static uint8_t convert_default_form_factor_to_module_type(void)
 }
 
 static uint8_t convert_ddrx_form_factor_to_module_type(smbios_memory_type memory_type,
-		smbios_memory_form_factor form_factor)
+						       smbios_memory_form_factor form_factor)
 {
 	uint8_t module_type;
 
@@ -213,8 +213,8 @@ static uint8_t convert_ddrx_form_factor_to_module_type(smbios_memory_type memory
 	case MEMORY_FORMFACTOR_RIMM:
 		return DDR2_SPD_RDIMM;
 	case MEMORY_FORMFACTOR_SODIMM:
-		module_type = (memory_type == MEMORY_TYPE_DDR2) ? DDR2_SPD_SODIMM
-				: DDR3_SPD_SODIMM;
+		module_type = (memory_type == MEMORY_TYPE_DDR2) ? DDR2_SPD_SODIMM :
+									DDR3_SPD_SODIMM;
 		return module_type;
 	default:
 		return convert_default_form_factor_to_module_type();
@@ -232,7 +232,7 @@ static uint8_t convert_lpx_form_factor_to_module_type(smbios_memory_form_factor
 }
 
 uint8_t convert_form_factor_to_module_type(smbios_memory_type memory_type,
-		smbios_memory_form_factor form_factor)
+					   smbios_memory_form_factor form_factor)
 {
 	uint8_t module_type;