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authorTim Wawrzynczak <twawrzynczak@chromium.org>2022-05-27 12:27:50 -0600
committerMartin L Roth <gaumless@tutanota.com>2022-05-29 14:46:02 +0000
commit2b83fa7741ab65bd6a77f8fcebfb5d9197eee921 (patch)
tree505889f6201eea048254b6b588e5de90e79265b7 /src/device
parent5027d2de4d63359967b02ba1aecc04b8f34b1d69 (diff)
device: Add IORESOURCE_ABOVE_4G flag to PCI64 resources
When a PCI resource is marked as 64-bits, the IORESOURCE_ABOVE_4G flag needs to be passed to the v4 allocator to ensure that the resource will be allocated in a range large enough to succeed. BUG=b:214443809 TEST=agah can successfully allocate all of the Nvidia GN20 BARs Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3f16f52f2a64f8728853df263da29871dca533f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Diffstat (limited to 'src/device')
-rw-r--r--src/device/pci_device.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 90b26c129b..fda088b020 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -423,7 +423,9 @@ static void configure_adjustable_base(const struct device *dev,
res->align = max_requested_bits;
res->gran = max_requested_bits;
res->limit = (res->flags & IORESOURCE_PCI64) ? UINT64_MAX : UINT32_MAX;
- res->flags |= IORESOURCE_PCIE_RESIZABLE_BAR;
+ res->flags |= (res->flags & IORESOURCE_PCI64) ?
+ IORESOURCE_PCIE_RESIZABLE_BAR | IORESOURCE_ABOVE_4G :
+ IORESOURCE_PCIE_RESIZABLE_BAR;
printk(BIOS_INFO, "%s: Adjusting resource index %lu: base: %llx size: %llx "
"align: %d gran: %d limit: %llx\n",