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authorFelix Singer <felix.singer@secunet.com>2020-09-07 15:21:21 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-11-16 12:14:01 +0000
commit205b53ee77baa257f20265dfbc6d6d72a2e504a5 (patch)
tree2df84a72949b92fa010a2b5b79c53c08b725061e /src/device
parent81f5bf301710911a5381084aba9ff99b8e575a46 (diff)
device: Allow configuring bus mastering for PCI bridges conditionally
Change-Id: Ic7cacce28f473dda76ca203016dbb8e00149a990 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/device')
-rw-r--r--src/device/Kconfig11
-rw-r--r--src/device/pci_device.c3
2 files changed, 13 insertions, 1 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 777f3f50d3..d564f00b9c 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -534,9 +534,20 @@ config PCI_ALLOW_BUS_MASTER
if PCI_ALLOW_BUS_MASTER
+config PCI_SET_BUS_MASTER_PCI_BRIDGES
+ bool "PCI bridges"
+ default y
+ help
+ Let coreboot configure bus mastering for PCI bridges. Enabling bus
+ mastering for a PCI bridge also allows it to forward requests from
+ downstream devices. Currently, payloads ignore this and only enable
+ bus mastering for the downstream device. Hence, this option is needed
+ for compatibility until payloads are fixed.
+
config PCI_ALLOW_BUS_MASTER_ANY_DEVICE
bool "Any devices"
default y
+ select PCI_SET_BUS_MASTER_PCI_BRIDGES
help
Allow coreboot to enable PCI bus mastering for any device. The actual
selection of devices depends on the various PCI drivers in coreboot.
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 6075ebeac7..f4608fc7f2 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -542,7 +542,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource)
dev->command |= PCI_COMMAND_MEMORY;
if (resource->flags & IORESOURCE_IO)
dev->command |= PCI_COMMAND_IO;
- if (resource->flags & IORESOURCE_PCI_BRIDGE)
+ if (resource->flags & IORESOURCE_PCI_BRIDGE &&
+ CONFIG(PCI_SET_BUS_MASTER_PCI_BRIDGES))
dev->command |= PCI_COMMAND_MASTER;
}