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authorAlexandru Gagniuc <alexandrux.gagniuc@intel.com>2016-05-23 12:16:58 -0700
committerMartin Roth <martinroth@google.com>2016-05-26 23:50:02 +0200
commitc4ea8f7d3fb56b43482b8abd8405280f50d98864 (patch)
treeff8598d2a4e12b65a2233e549d4a1f442f030428 /src/device
parentc16918ac11c32338ba99656ec47ca05e26a731ac (diff)
drivers/intel/fsp2_0: Send post codes around calls to the blobs
By design, FSP will send POST codes to port 80. In this case we have both coreboot and FSP pushing post codes, which may make debugging harder. In order to get a clear picture of where FSP execution begins and ends, send post codes before and after any call to the FSP blobs. Note that sending a post code both before and after is mostly useful on chromeec enabled boards, where the EC console will provide a historic list of post codes. Change-Id: Icfd22b4f6d9e91b01138f97efd711d9204028eb1 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14951 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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