diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-24 17:37:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-04 23:09:22 +0000 |
| commit | bccb6916feffa340be163cefa2654e014c485b79 (patch) | |
| tree | 1709df9da0b2ea38ca74fc0a43009404f3b35cd1 /src/device | |
| parent | b513c53f31678a51111df3b7313dafb976854074 (diff) | |
security/intel/txt/ramstage.c: Fix clearing secrets on CBNT
intel_txt_memory_has_secret() checks for ESTS.TXT_ESTS_WAKE_ERROR_STS
|| E2STS.TXT_E2STS_SECRET_STS and it looks like with CBNT the E2STS
bit can be set without the ESTS bit.
Change-Id: Iff4436501b84f5c209add845b3cd3a62782d17e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47934
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device')
0 files changed, 0 insertions, 0 deletions