summaryrefslogtreecommitdiff
path: root/src/device/smbus_ops.c
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2016-12-12 10:43:45 -0800
committerDuncan Laurie <dlaurie@chromium.org>2016-12-14 01:46:05 +0100
commit93eb8c48b654ab100491822212238909fa1a2962 (patch)
tree92d9e7260b984343571f3efdbc90d35ec0c10c16 /src/device/smbus_ops.c
parentb7a52d3cd6d241c4c88028deea19a5de04c34a95 (diff)
google/eve: Configure I2C3 pins as GPIO inputs
On this board i2c3 bus is connected to the display TCON, but it is acting as the master when it has power so it can read from its own EEPROM on the bus. In order to prevent any possible issues in S0 make these pins input on the SOC. BUG=chrome-os-partner:58666 TEST=tested on eve board, but this bus was not used before so there is no visible change in behavior. Change-Id: Ide32f45ee33ca986fd3249a5161e01edf99d6e22 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17800 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/device/smbus_ops.c')
0 files changed, 0 insertions, 0 deletions