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authorArthur Heymans <arthur@aheymans.xyz>2023-08-24 15:12:19 +0200
committerFelix Held <felix-coreboot@felixheld.de>2024-01-31 10:36:39 +0000
commit7fcd4d58ec7ea2da31c258ba9d8601f086d7f8d8 (patch)
tree1bddf10cecf4577fee207e0dbc6f7a5c1b10af13 /src/device/pcix_device.c
parent3138faa7cf1b91e0b56ad0b1be6260cf4251a284 (diff)
device/device.h: Rename busses for clarity
This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/device/pcix_device.c')
-rw-r--r--src/device/pcix_device.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c
index e40ed3bf65..7ddc15d4eb 100644
--- a/src/device/pcix_device.c
+++ b/src/device/pcix_device.c
@@ -107,11 +107,11 @@ void pcix_scan_bridge(struct device *dev)
sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
if (PCI_X_SSTATUS_MFREQ(sstatus) != PCI_X_SSTATUS_CONVENTIONAL_PCI)
- pcix_tune_bus(dev->link_list);
+ pcix_tune_bus(dev->downstream);
/* Print the PCI-X bus speed. */
- printk(BIOS_DEBUG, "PCI: %02x:%02x: %s\n", dev->link_list->segment_group,
- dev->link_list->secondary, pcix_speed(sstatus));
+ printk(BIOS_DEBUG, "PCI: %02x:%02x: %s\n", dev->downstream->segment_group,
+ dev->downstream->secondary, pcix_speed(sstatus));
}
/** Default device operations for PCI-X bridges */