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author | Subrata Banik <subratabanik@google.com> | 2024-02-20 20:19:13 +0530 |
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committer | Subrata Banik <subratabanik@google.com> | 2024-02-25 03:57:10 +0000 |
commit | 259fc2b1190f23af085773a23a9c79209d3394c4 (patch) | |
tree | b3ab18849a2a1ed0692e1ad4d7274fdb95ca8f6d /src/device/pciexp_device.c | |
parent | 9305ccada13986d21ffaf874507f2d811d1ebe7b (diff) |
mb/google/rex/var/deku: Refactor SSD power sequencing
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/deku using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: Iedaff8a793f1ba5d2b97352b95c4dfdd2b818ebd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80664
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pciexp_device.c')
0 files changed, 0 insertions, 0 deletions