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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-08 22:55:12 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-17 16:24:16 +0000 |
| commit | 75547dbc53cde54dc83e26ef22828ce7cf9e2ba2 (patch) | |
| tree | e9535df7e3fe89544942ac4326e3bf1cac320984 /src/device/pciexp_device.c | |
| parent | 9c4514ba14e29550041e4c18aaafdd7c0bbc097e (diff) | |
soc/amd/common/fsp: add common CPPC data HOB support
Add common AMD FSP functionality to get the nominal and minimal CPU core
CPPC frequencies. Those functions will be used in the _CPC ACPI object
generation in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Change-Id: I68ebdf610795d2673e0118a732f54f5f719b73c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66550
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pciexp_device.c')
0 files changed, 0 insertions, 0 deletions