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authorSubrata Banik <subratabanik@google.com>2023-04-06 15:12:22 +0530
committerSubrata Banik <subratabanik@google.com>2023-04-11 11:38:23 +0000
commit9629f94c4e7acd50a198cdec90418e3a2405127c (patch)
tree0752cdd8e436bc35956d07032256371480158fc2 /src/device/pci_rom.c
parentcda48b297c75ca79a956bb2033c5ed28e426543c (diff)
mb/google/rex: Update Flash Layout to fit WP_RO within 4MB
This patch updates the Rex flash layout to optimize WP_RO to 4MB. The idea is to create more space inside FW_RW_A/B to accommodate multiple blobs to boot google/rex with different Intel MTL SoC stepping. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74229 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/device/pci_rom.c')
0 files changed, 0 insertions, 0 deletions