diff options
| author | pchandri <preetham.chandrian@intel.com> | 2015-11-30 13:05:53 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-15 12:03:55 +0100 |
| commit | ff25b7532caa37f6ebb42d9485cbe805c5aec2d1 (patch) | |
| tree | 636766f05271a07e2cc1bba50f186957c5530cd9 /src/device/pci_rom.c | |
| parent | fbc4609265dab70e09b2f59e4f93f60f81c110c4 (diff) | |
intel/kunimitsu: Enable 20K PU on LPC_LAD 0-3
At S0, S0ix and S3 LPC LAD signals are
are floated at 400~500mV.
BRANCH=chrome-os-partner:48331
BUG=None
TEST=Build and Boot kunimitsu
Change-Id: I2e2654ac89f8e0c8d6ab1af31d0bd5a0d4c43db8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6f4b902e220dcde73df56970208c45fe3148b70e
Original-Change-Id: I597d4816d09d0cfd9b0ec183a9273551aed8688a
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316529
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://review.coreboot.org/12957
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/device/pci_rom.c')
0 files changed, 0 insertions, 0 deletions