diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2015-11-02 18:58:36 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-15 20:40:05 +0100 |
| commit | b57772d2bf117e81b9e3cbb9d08ffbfae581ba69 (patch) | |
| tree | ad1e7fc54af188c2d9199f242d2395b59e96a026 /src/device/pci_rom.c | |
| parent | ff25b7532caa37f6ebb42d9485cbe805c5aec2d1 (diff) | |
intel/skylake: Update UPD parameters as per FSP 1.8.0
Some MemoryInit UPD parameters have been moved to
SiliconInit in FSP 1.8.0. This patch has the respective
changes in coreboot for this.
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu
CQ-DEPEND=CL:*237423, CL:*237424
Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118
Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310191
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/device/pci_rom.c')
0 files changed, 0 insertions, 0 deletions