diff options
author | Subrata Banik <subratabanik@google.com> | 2024-09-17 15:38:42 +0530 |
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committer | Subrata Banik <subratabanik@google.com> | 2024-09-18 14:23:55 +0000 |
commit | 7ece43aeb5c5c10a9dcea8d05418b457e5d2f158 (patch) | |
tree | 1feead4471dc665d15f777cf34bccae45f692376 /src/device/pci_rom.c | |
parent | b8e8d078fc803a92d18737c3d68ac2c07ec2fabf (diff) |
soc/intel: Move CSE update ELOG to cse_lite.c
The ELOG for CSE updates was being added in fsp_params.c, but the
actual update happens in cse_lite.c. This commit moves the ELOG to
cse_lite.c to more accurately reflect where the event is happening.
This also removes the need for a sol_type variable in
meteorlake/romstage/fsp_params.c.
It also helps to avoid redundant ELOG event entry while performing
CSE update (due to CSE RO to RW switch dependency).
BUG=b:361253028 (Multiple CSE sync elog prints for Nissa/Trulo)
TEST=Able to see only one instance of ELOG while performimg CSE sync.
w/o this patch:
elogtool list
0 | Log area cleared | 4088
1 | Kernel Event | Clean Shutdown
2 | Early Sign of Life | MRC Early SOL Screen Shown
3 | Early Sign of Life | CSE Sync Early SOL Screen Shown
4 | System boot | 29
5 | Memory Cache Update | Normal | Success
6 | Early Sign of Life | CSE Sync Early SOL Screen Shown
w/ this patch:
elogtool list
0 | Log area cleared | 4088
1 | Early Sign of Life | MRC Early SOL Screen Shown
2 | Memory Cache Update | Normal | Success
3 | System boot | 30
4 | Memory Cache Update | Normal | Success
5 | Early Sign of Life | CSE Sync Early SOL Screen Shown
Change-Id: I37fe3f097e581f79bf67db1ceb923f10ce651d62
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Diffstat (limited to 'src/device/pci_rom.c')
0 files changed, 0 insertions, 0 deletions