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author | Mike Loptien <mike.loptien@se-eng.com> | 2013-02-25 10:41:28 -0700 |
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committer | Dave Frodin <dave.frodin@se-eng.com> | 2013-02-25 19:28:43 +0100 |
commit | a96d24d672abfd2ce91caa2d762fdce3d67da600 (patch) | |
tree | ff526a651f8b2975193f6f0b8e56830fa9b38271 /src/device/pci_ops.c | |
parent | 7675d8a481c6cbeba418f00f2eb733d904171a41 (diff) |
AMD Southbridge: Add RTC init to lpc_init
Adding RTC init code to the Southbridge initialization
code in 'lpc_init'. This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup. By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts
This is the same edit made to the CIMX SB800 titled
'AMD/Persimmon: Add RTC init to CIMX SB800' with commit
ID: c4d3d which can be viewed here:
http://review.coreboot.org/#/c/2488/
Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2510
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Diffstat (limited to 'src/device/pci_ops.c')
0 files changed, 0 insertions, 0 deletions