diff options
author | Aaron Durbin <adurbin@chromium.org> | 2015-08-05 14:33:37 -0500 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-14 15:18:19 +0200 |
commit | a0429b6f3ca6aa63124dbbbe3507629adc9ccd23 (patch) | |
tree | ad369bfbbe089b37d9b7f0fca429963a9aae8d49 /src/device/pci_ops.c | |
parent | 6f4c7a6fded85c4687386b857687af4b9a953851 (diff) |
skylake: clean up SMM region calculations
The TSEG is defined to be from TSEG->BGSM in the
host bridge registers. Use those registers at
runtime to calculate the correct TSEG size.
Lastly, use a few helper macros to make constants
more readable.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290832
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11195
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/device/pci_ops.c')
0 files changed, 0 insertions, 0 deletions